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lihlahisoa

10AX115H2F34E2SG FPGA Arria® 10 GX Lelapa 1150000 Lisele 20nm Technology 0.9V 1152-Pin FC-FBGA

tlhaloso e khuts'oane:

10AX115H2F34E2SG lelapa la lisebelisoa le na le ts'ebetso e phahameng le e sebetsang hantle ea 20 nm bohareng ba FPGAs le SoCs.

Ts'ebetso e phahameng ho feta moloko o fetileng oa mahareng le maemo a holimo
FPGAs


Lintlha tsa Sehlahisoa

Li-tag tsa Sehlahisoa

Litlhaloso tsa Teknoloji ea Sehlahisoa

EU RoHS

E lumellana

ECCN (US)

3A991

Boemo ba Karolo

E sebetsa

HTS

8542.39.00.01

SVHC

Ee

SVHC e Feta Tekanyo

Ee

Tsa makoloi

No

PPAP

No

Lebitso la lelapa

Arria® 10 GX

Theknoloji ea Ts'ebetso

20nm

Li-I/Os tsa basebelisi

504

Palo ea Lingoliloeng

1708800

Motlakase oa Phepelo ea Ts'ebetso (V)

0.9

Lintlha tse utloahalang

1150000

Palo ea Ba bangata

3036 (18x19)

Mofuta oa Memori ea Lenaneo

SRAM

Memori e kentsoeng (Kbit)

54260

Kakaretso ea Nomoro ea Block RAM

2713

EMACs

3

Lisebelisoa tsa Logic ea Sesebelisoa

1150000

Nomoro ea lisebelisoa tsa DLLs/PLL

32

Likanale tsa Transceiver

96

Lebelo la Transceiver (Gbps)

17.4

DSP e inehetseng

1518

PCIe

4

Programmability

Ee

Tšehetso ea Reprogrammability

Ee

Kopitsa Tšireletso

Ee

In-System Programmability

Ee

Lebelo Kereiti

2

Maemo a I/O a nang le Qetello e le 'Ngoe

LVTTL | LVCMOS

Sehokelo sa Memori sa kantle

DDR3 SDRAM|DDR4|LPDDR3|RLDRAM II|RLDRAM III|QDRII+SRAM

Minimum Operating Supply Voltage (V)

0.87

Maximum Operating Supply Voltage (V)

0.93

I/O Voltage (V)

1.2|1.25|1.35|1.5|1.8|2.5|3

Mocheso o fokolang oa ho sebetsa (°C)

0

Thempereichara e Holimo ea Tšebetso (°C)

100

Supplier Temperature Kereiti

Eketsehile

Lebitso la khoebo

Arria

Ho phahamisa

Thaba e kaholimo

Bophahamo ba Sephutheloana

2.95

Bophara ba Sephutheloana

35

Bolelele ba Sephutheloana

35

PCB e fetohile

1152

Lebitso la Sephutheloana se Tloaelehileng

BGA

Sephutheloana sa Bafani

FC-FBGA

Palo ea Pin

1152

Lead Shape

Bolo

Phapang le kamano lipakeng tsa FPGA le CPLD

1. Tlhaloso le litšobotsi tsa FPGA

FPGAe amohela mohopolo o mocha o bitsoang Logic Cell Array (LCA) le Configurable Logic Block (CLB) le Input Output (IOB) Block le Interconnect.The configurable logic module ke yuniti ea mantlha ea ho hlokomela ts'ebetso ea mosebelisi, eo hangata e hlophisoang ka bongata le ho hasanya chip kaofela.Mojule oa li-input-output IOB o phethela khokahano lipakeng tsa logic ho chip le pini ea sephutheloana sa kantle, 'me hangata e hlophisoa ho potoloha chip array.Wiring e ka hare e na le bolelele bo fapaneng ba likarolo tsa terata le li-switches tse ling tse lokiselitsoeng, tse hokahanyang li-block tsa logic tse fapaneng kapa li-block tsa I/O ho theha potoloho e nang le ts'ebetso e itseng.

Likarolo tsa mantlha tsa FPGA ke:

  • Ho sebelisa FPGA ho qapa potoloho ea ASIC, basebelisi ha ba hloke ho etsa tlhahiso ea morero, ba ka fumana chip e loketseng;
  • FPGA e ka sebelisoa e le sampole ea sefofane ea tse ling tse hlophisitsoeng ka botlalo kapa tse hlophisitsoeng hantleLipotoloho tsa ASIC;
  • Ho na le lintho tse ngata tse susumetsang le li-Pins tsa I/O ho FPGA;
  • FPGA ke e 'ngoe ea lisebelisoa tse nang le potoloho e khuts'oane ea moralo, litšenyehelo tse tlase tsa nts'etsopele le kotsi e tlase ho potoloho ea ASIC.
  • FPGA e amohela ts'ebetso e potlakileng ea CHMOS, tšebeliso e tlase ea matla, 'me e ka tsamaellana le maemo a CMOS le TTL.

2, tlhaloso le litšobotsi tsa CPLD

CPLDhaholo-holo e entsoe ka Logic Macro Cell (LMC) e hlophisitsoeng ho potoloha setsi sa "programmable interconnection matrix unit", moo sebopeho sa LMC logic se rarahaneng haholoanyane, 'me se na le sebopeho se rarahaneng sa I/O sa khokahano ea yuniti, se ka hlahisoang ke mosebelisi ho latela litlhoko tsa sebopeho se itseng sa potoloho, ho phetha mesebetsi e itseng.Hobane li-block tsa logic li hokahane le lithapo tsa tšepe tsa bolelele bo tsitsitseng ho CPLD, potoloho ea logic e hlophisitsoeng e na le ts'ebetso ea nako esale pele mme e qoba bokhopo ba ho bolela esale pele ho sa phethahalang ha nako ea sebopeho sa khokahano e arohaneng.Lilemong tsa bo-1990, CPLD e ile ea ntlafala ka potlako, eseng feela ka litšoaneleho tsa ho hlakola motlakase, empa hape le ka likarolo tse tsoetseng pele tse kang ho hlahloba moeli le mananeo a marang-rang.

Litšobotsi tsa lenaneo la CPLD ke tse latelang:

  • Lisebelisoa tse utloahalang le tsa memori li ngata (Cypress De1ta 39K200 e na le ho feta 480 KB ea RAM);
  • Mokhoa o feto-fetohang oa nako o nang le lisebelisoa tse ngata tsa ho tsamaisa litsela;
  • Flexible ho fetola tlhahiso ea pin;
  • E ka kenngoa tsamaisong le ho hlophisoa bocha;
  • Palo e kholo ea likarolo tsa I/O;

3. Liphapang le likamano lipakeng tsa FPGA le CPLD

CPLD ke khutsufatso ea sesebelisoa sa logic se rarahaneng, FPGA ke khutsufatso ea "field programmable gate array", ts'ebetso ea tse peli e ts'oana, empa molao-motheo oa ts'ebetsong o fapane hanyane, kahoo ka linako tse ling re ka hlokomoloha phapang lipakeng tsa tse peli, ka kopanelo. e bitsoa sesebelisoa sa logic kapa CPLD/FPGA.Ho na le lik'hamphani tse 'maloa tse hlahisang CPLD/FPGas, tse tharo tse kholo ka ho fetisisa ke ALTERA,XILINX, le LAT-TICE.CPLD decomposition combinatorial logic function e matla haholo, yuniti e kholo e ka senya 12 kapa ho feta 20-30 combinatorial logic input.Leha ho le joalo, LUT ea FPGA e khona ho sebetsana le mohopolo o kopaneng oa likenyelletso tse 4, ka hona CPLD e loketse ho rala mohopolo o kopaneng o kopaneng joalo ka decoding.Leha ho le joalo, ts'ebetso ea tlhahiso ea FPGA e etsa qeto ea hore palo ea LUTs le li-trigger tse ka har'a chip ea FPGA li kholo haholo, hangata likete tse likete, CPLD ka kakaretso e ka finyella likarolo tse utloahalang tsa 512, 'me haeba theko ea chip e aroloa ka palo e utloahalang. li-unit, karolelano ea theko ea yuniti ea FPGA e tlase haholo ho feta ea CPLD.Kahoo haeba ho sebelisoa lintho tse ngata tse susumetsang moralong, joalo ka ho rala logic e rarahaneng ea nako, joale ho sebelisa FPGA ke khetho e ntle.

Leha FPGA le CPLD ka bobeli e le lisebelisoa tsa ASIC tse hlophisehang 'me li na le litšobotsi tse ngata tse tšoanang, ka lebaka la phapang ea sebopeho sa CPLD le FPGA, li na le litšobotsi tsa tsona:

  • CPLD e loketse haholoanyane bakeng sa ho phethela li-algorithms tse fapaneng le logic ea combinatorial, 'me FPGA e loketse ho tlatsa logic e latellanang.Ka mantsoe a mang, FPGA e loketse haholoanyane bakeng sa sebopeho se ruileng sa flip-flop, ha CPLD e loketse haholoanyane bakeng sa sebopeho se lekanyelitsoeng sa flip-flop le sehlahisoa sa nako e telele ea sehlahisoa.
  • Sebopeho se sa khaotseng sa CPLD se etsa qeto ea hore ho lieha ha nako hoa tšoana ebile ho ka lebelloa, ha sebopeho sa FPGA se arotsoe ka tsela e etsang qeto ea hore tieho ea eona e ke ke ea lebelloa.
  • FPGA e na le maemo a bonolo ho feta CPLD lenaneong.
  • CPLD e hlophisitsoe ka ho fetola ts'ebetso ea logic ea potoloho e tsitsitseng ea ka hare, ha FPGA e hlophisitsoeng ka ho fetola mohala oa khokahanyo ea ka hare.
  • Fpgas e ka hlophisoa tlas'a liheke tsa logic, ha CPLDS e hlophisitsoe tlas'a li-block blocks.
  • FPGA e hokahane ho feta CPLD mme e na le sebopeho se rarahaneng sa lithapo le ts'ebetsong ea kelello.

Ka kakaretso, tšebeliso ea matla ea CPLD e kholo ho feta ea FPGA, 'me ha tekanyo ea ho kopanya e phahame, e hlakile haholoanyane.


  • E fetileng:
  • E 'ngoe:

  • Ngola molaetsa wa hao mona mme o re romele wona